This invention relates to a nonvolatile semiconductor memory device comprising a nonvolatile transistor and allowing the stored data to be replaced by another data.
This type of nonvolatile semiconductor memory device is well known as an E.sup.2 ROM (electrically erasable and programmable read only memory). One known memory cell for use in the E.sup.2 PROM, is a floating gate type memory cell, in which the floating gate electrode partially overlaps a thin insulating film formed on the diffusion layer.
FIG. 1 is a sectional view showing the structure of a prior art memory cell of this type. N type diffusion layers 41, 42 and 43 are formed in the surface region of P type semiconductor substrate 40. Channel region 44 is formed between diffusion layers 41 and 42. A relatively thick insulating film 45 is formed on channel region 44. Electrode 46 made of polysilicon is formed on the insulating layer 45. Electrode 46 extends over N type diffusion layer 42. A portion of electrode 46 projects toward diffusion layer 42. Insulating film 47 exists between diffusion layer 42 and a portion of electrode 46. Insulating film 47 is thinner than insulating film 45. Insulating film 48 is formed on electrode 46. Electrode 49 made of polysilicon is formed on insulating film 48.
Channel region 50 is also formed between diffusion layers 42 and 43. Relatively thick insulating film 51 is formed on channel region 50. Further, electrode 52 made of polysilicon is formed on insulating film 51.
Source interconnection S is connected to diffusion layer 41, and bit line BL is connected to diffusion layer 43. Electrode 46 is used as a floating gate electrode, and electrode 49 is used as a control gate electrode, and electrode 52 is used as a gate electrode. Control gate electrode 49 is connected to control gate wire CG, and select gate wire SG is connected to gate electrode 52.
FIG. 2 shows an equivalent circuit of the prior art memory cell shown in FIG. 1. As is shown in the figure, transistor 61 is of the floating gate type in which diffusion layers 41 and 42 are a source and a drain, respectively. This transistor constitutes a memory transistor for storing data. Transistor 62 is of the MOS type in which diffusion layers 42 and 43 are a source and a drain, respectively. This transistor is for selecting memory transistor 61.
Operation modes of such memory cells includes a data-erase mode, a data-write mode and a data-read mode. FIG. 3 tabulates the voltages applied to source interconnection S, bit line BL, control gate wire CG, and selecting gate wire SG. Three types of power source voltages are used in the integrated circuit including the E.sup.2 PROM: GND, Vcc and Vpp. GND=0 V, and Vcc=5 V. Power source voltage Vpp is not supplied from an external power supply, but formed by increasing the Vcc voltage in the IC circuit.
The data-erase mode will first be described. This mode is also called an electron injection mode. In the mode, electrons are injected into floating gate electrode 46 to increase the threshold voltage V.sub.TH of memory transistor 61. In this mode, BL=0 V, SG=20 V, CG=20 V, and S=0 V. By setting SG voltage at 20 V, selecting transistor 62 is turned on, and the potential at N type diffusion layer 42 becomes the BL potential, i.e., 0 V. Floating gate electrode 46 is coupled with a high voltage of CG, 20 V. Under this condition, a high electric field is applied to thin insulating film 47 formed between floating gate electrode 46 and N type diffusion layer 42. Consequently, floating gate electrode 46 is injected with electrons from N type diffusion layer 42 by a tunnel current. As a result, the threshold voltage V.sub.TH of memory transistor 61 increases to, for example, +8 V.
The data-write mode is called an electron-emission mode in which electrons injected into floating gate electrode 46 are discharged therefrom to decrease the threshold voltage V.sub.TH of memory transistor 61. In this mode, BL=20 V, SG=20 V, CG=0 V, and S=5 V. By setting SG at 20 V, selecting transistor 62 is turned on, and N type diffusion layer 42 becomes the BL potential, i.e., 20 V. Therefore, a high electric field whose direction is opposite to that of the erase mode, is applied to thin insulating film 47 Consequently, the electrons are discharged from floating gate electrode 46 to N type diffusion layer 42. As a result, the threshold voltage V.sub.TH of memory transistor 61 decreases to, for example, -5 V.
In the data-read mode, BL=1 V, SG=5 V, CG=0 V, and S=0 V. By setting SG at 5 V, selecting transistor 62 is turned on, and N type diffusion layer 42 becomes the BL potential, i.e., 1 V. At this time, if electrons have been injected into floating gate electrode 46, the threshold voltage of memory transistor 61 has been increased. Therefore, memory transistor 61 is kept turned off. No current flows through BL and S, and BL is kept at 1 V. On the other hand, if electrons have been emitted from floating gate electrode 46, the threshold voltage of memory transistor 61 has been descreased. Therefore, transistor 61 is turned on. At this time, a current flows from floating gate electrode 46 toward N type diffusion layer 42, and the potential of BL becomes the S potential, i.e., approximately 0 V. A potential difference between 1 V and 0 V on bit line BL is amplified by a sense amplifier (not shown) connected to bit line BL, to determine a logical "1" or a logical "0".
An existing problem arises from the fact that a small potential difference between 1 V and 0 V occurring on bit line BL is amplified by a sense amplifier. In other words, a small potential difference is used, in order to determine a logical "1" or a logical "0" by a sense amplifier.
The reason why the bit line voltage BL must be held at about 1 V, and not at large voltage 5 V, in the read mode, will be described. When BL=5 V, the voltage of N type diffusion layer 42 becomes approximately 5 V. Under this condition, an electric field, which is caused by CG=0 V and N type diffusion layer 42=5 V, is applied to thin insulating film 47. When the electric fields in the read and write modes are compared, the directions of the electric fields are the same, but the intensities are different. The electric field intensity in the read mode is lower than that in the write mode. Therefore, when electrons are injected into the cell transistor, and the cell transistor is subjected to the read mode for a long time, electrons are emitted from the cell transistor due to the tunnel effect with time, so that the threshold voltage of the cell transistor gradually drops. When a certain period of time has elapsed, an erroneous logical operation may be caused in the circuit. Such a phenomenon is called a "soft write" (weak write) phenomenon. The characteristic of the soft write phenomenon with respect to the time is called a read-retention characteristic (the data-retention characteristic in the read mode).
A possible way to improve the read-retention characteristic is to decrease the bit line voltage in the read mode. In this approach, however, a difference between the bit line potential when the electrons are being injected into the cell transistor and the bit line potential when electrons are emitted from the cell transistor, is small, to narrow the logical margin in the read mode. For this reason, the bit line potential in the read mode is limited to about 1 V.
On the other hand, to cope with the small logical margin problem, a high performance sense amplifier is designed. However, this causes some problems. A first problem resides in the complicated circuit of the sense amplifier. To fabricate such a complicated amplifier circuit into a semiconductor chip, a large area is required on the semiconductor chip, resulting in increase of cost of manufacture. A second problem resides in the reduced margin for the power source voltage in the read mode. This is undesirable for the low voltage operation. A third problem resides in the need for the constant voltage source of 1 V (intermediate voltage) to be supplied to the bit line. The prior art memory device must comprise a circuit for forming such an intermediate voltage, resulting in increase of power consumption. A fourth problem resides in a long access time due to the complicated structure of the sense amplifier.
As described above, the prior art nonvolatile memory device involves many problems; the large area required on the semiconductor chip, instable low voltage operation, large power consumption, and the long access time.